1. Field of the Invention
The present invention relates to a memory device, and in particular, to a semiconductor memory device.
2. Background of the Related Art
FIG. 1 illustrates a memory cell array and a sense amplifier in a related art memory device, e.g., DRAM. The memory cell array and sense amplifier of the related art DRAM includes a sense amplifier driving unit 10 for receiving sense amplifier enabling signals SN and SPB and a sense amplifier equalizing signal SAEQ and sense amplifiers 11-14. The sense amplifiers 11-14 are driven by the sense amplifier driving unit 10 and connected with respective pairs of bit lines BL0-BLm and BL0b-BLmb. The memory cell array and sense amplifier further includes pre-charge units 15-18 for pre-charging the bit lines BL0-BLm to a level corresponding to one-half of the supply voltage Vcc in accordance with a bit line equalizing signal BLEQ and a pre-charge signal line VLBP and a memory cell array 19 having a plurality of cells 19a and 19b connected with word lines WL0-WLn and the bit lines BL0-BLm and BL0b-BLmb. The memory cell array 19 is configured in a folded form. In other words, the cells 19a and 19b are formed on either the bit lines BL0-BLm and BL0b-BLmb.
The sense amplifier driving unit 10 includes a PMOS transistor 10a. The gate of the PMOS transistor 10a receives the sense amplifier enabling signal SPB, the source receives the supply voltage Vcc and the drain is connected with a signal line SPC to the sense amplifiers 11 through 14. An NMOS transistor 10b has the drain connected with the drain of PMOS transistor 10a and the signal line SPC. The gate of the NMOS transistor 10b receives the sense amplifier equalizing signal SAEQ, and the source is connected with a signal line SNCB to the sense amplifiers 11 through 14. An NMOS transistor 10c has the drain connected with the source of the NMOS transistor 10b and the signal line SNCB, the gate receives the sense amplifier enabling signal SN, and the source is connected to ground supply voltage Vss.
The sense amplifier 11 includes PMOS transistors 11a and 11b. The sources of the PMOS transistors 11a and 11b are commonly connected with the signal line SPC and the respective gates are connected with the bit lines BL0b and BL0, and with the drain of their counterpart PMOS transistor. The sources of NMOS transistors 11c and 11d are commonly connected with the signal line SNCB. The drains of the NMOS transistors 11c and 11d are connected to the drains of the PMOS transistors 11a, 11b, respectively, and the respective gates are connected the drain of their counterpart NMOS transistor and with the bit lines BL0b and BL0, respectively. The remaining sense amplifiers 12 through 14 have the same construction as the sense amplifier 11.
The pre-charge unit 15 includes an NMOS transistor 15a, the drain and source of which are respectively connected with the bit lines BL0 and BL0b, and the gate of which is connected with a bit line equalizing signal BLEQ line and gates of NMOS transistors 15b and 15c. The sources of the NMOS transistors 15b and 15c are commonly connected to the pre-charge signal VLBP line, the gates are connected with the bit line equalizing signal BLEQ line and the respective drains are connected to the bit lines BL0 and BL0b, respectively. The remaining pre-charge units 16 through 18 have the same construction as the pre-charge unit 15.
As shown in FIG. 2, the interface unit for driving the memory cell array and sense amplifiers of the related art DRAM includes an address multiplexor 20 for multiplexing address signal bits Ai and Aj in accordance with a row address strobe signal /RAS and a row address resetting unit 21. The interface unit further includes for resetting the output signal from the address multiplexor 20 in accordance with the row address strobe signal /RAS and a pre-decoder 22 for decoding the output signal from the row address resetting unit 21. The interface unit further includes a row decoder 23 for decoding the output signal from the pre-decoder 22, a word line driving unit 24 for receiving the output signal from the row decoder 23 and for driving the word lines WL0 through WLn, a block decoder 25 for decoding the output signal from the pre-decoder 22, and a sense amplifier controller 26 for receiving the output signal from the block decoder 25. The sense amplifier controller 26 also applies the sense amplifier enabling signals SN and SPB and the sense amplifier equalizing signal SAEQ to the sense amplifier driving unit 10 as shown in FIG. 1.
The address multiplexor 20 includes an inverter 20a for inverting the row address strobe signal /RAS, a transmission gate 20b for switching the address signal bit Ai line in accordance with the row address strobe signal /RAS and the inverted signal RAS from the inverter 20a and inverters 20c and 20d for latching the output signal from the transmission gate 20b. The address multiplexor 20 further includes a transmission gate 20e for switching the address signal bit line Aj in accordance with the row address strobe signal /RAS, and inverters 20f and 20g for latching the output signal from the transmission gate 22e. The remaining address signal bit lines have the same associated circuitry as the bit line Aj.
The row address resetting unit 21 includes NOR-gates 21a through 21d for each NORing the row address strobe signal /RAS and the output signals of inverters 20c and 20d from the address multiplexor 20. Each pre-decoder 22, as shown in FIG. 3, includes NAND-gates 22a through 22d for selecting 1 valid output signal "Low" from the row address resetting unit 21, and inverters 22e through 22h for inverting the respective output signals of the NAND-gates 22a through 22d.
For example, while /RAS is "Low" if the output signal of the NOR gate 21a is "High" and the output signal of the NOR gate 21c is "Low", the output signal of the NOR gate 21b becomes "Low" and the output signal of the transmission gante 20b becomes "High".
So only the output signal of the pre-decoder 22c becomes "Low" and the other 3 signals become "High".
In case /RAS is "High", NOR gates 21a,b,c,d become "High" and pre-decoders 22e,f,g,h become "Low".
The operation of the related art DRAM will now be described. When the row address strobe signal /RAS, as shown in FIG. 4A, is transited (asserted), the address signal, as shown in FIG. 4B, is inputted into the address multiplexor 20. The row address passed through the address multiplexor 20 is applied to the pre-decoder 22 through the row address resetting unit 21, and if the row address strobe signal /RAS is high level, the row address signal is reset by the row address resetting unit 21.
The pre-decoder 22 decodes the row address inputted and outputs the row address to the row decoder 23 and the block decoder 25, respectively. Therefore, in the word line driving unit 24, a high level signal is carried on the word line WLi corresponding to the row address, and the bit line corresponding to the address signal is selected.
The sense amplifier controller 26 outputs sense amplifier enabling signals SN and SPB and sense amplifier equalizing signal SAEQ to activate the sense amplifier driving unit 10 so that the data of a corresponding cell of the memory array 19 is read. Thereafter, the row address strobe signal /RAS is again transited to a low level, and the signal of the word line WLi is transited to a low level. In addition, the bit lines BL0 through BLm and BL0b through BLmb are pre-charged as much as one-half of the voltage Vcc in accordance with the pre-charge signal VBLP.
When the row address strobe signal /RAS is again transited (asserted) another address signal is inputted. Therefore, the word line WLj corresponding to the new address signal is activated. In the related art DRAM, whenever the address is changed, the bit lines BL0 through BLm and BL0b through BLmb are always pre-charged so that the data of the next addressed memory location is not combined with the previous data.
However, the related art DRAM has various disadvantages. Since the bit lines BL0 through BLm and BL0b through BLmb are always pre-charged when the address is changed, it is not possible to write the data corresponding to the previous address and stored in the sense amplifier into the memory cell of another address via the common bit line.